The present invention generally relates to a method for fabricating interconnection structure in an integration circuit, and more specifically to a method for fabricating vias and trenches in a dual-damascene multilevel interconnection structure of an integration circuit.
Wiring trenches and via holes are formed conventionally in the inter-layer insulating materials for multilevel metal interconnection microelectronics. To simplify the manufacturing process, both the vias and trenches are formed by a single process step. This single process step is called a xe2x80x9cdual-damascenexe2x80x9d process. When trench patterns are etched before etching the via holes, the process is called a xe2x80x9ctrench-firstxe2x80x9d dual-damascene process. On the other hand, when via holes are etched before the etch of the trench patterns, the process sequence is called xe2x80x9cvia-firstxe2x80x9d. Trenches and vias are formed conventionally by removing dielectric material being deposited on a dielectric layer using a plasma-etching method in a semiconductor manufacturing process. However, this method has some difficulties, especially in a dual-damascene process for multilevel metal interconnection microelectronics no matter whether the via-first or trench-first method is used. If only a single dielectric layer is used as the inter-metal dielectric (IMD) layer in a via-first or trench-first dual-damascene process without using any etch stop layer (ESL), then the manufacturing result is poor. Therefore, etch stop layers are commonly used as the inter-metal dielectric layers in a conventional dual-damascene process. However, adding etch stop layers greatly increases not only the processing steps but also the complexity of the dual-damascene process. Moreover, because the etch stop layer usually uses a material of high dielectric constant, the performance of the semiconductor device is degraded.
U.S. Pat. No. 6,096,655 discloses a method for forming vias and trenches in an insulation layer for a dual-damascene multilevel interconnection structure. It comprises the following steps: depositing a first sacrificial layer, etching the sacrificial layer, depositing a first inter insulation layer, depositing a second sacrificial layer, depositing a second inter insulation layer, and selectively etching the second sacrificial layer and forming vias and trenches simultaneously. Referring to FIGS. 1a-1g, this method uses reversed via and trench patterns in the inter-insulation layer for a dual-damascene process to replace commonly used masks. As shown in FIG. 1a, a silicon film of polycrystalline or amorphous used as a sacrificial layer 12 is deposited over a dielectric layer 11 on a substrate 10. A photo-resist mask 13 is deposited to form a reverse pattern of the vias as shown in FIG. 1b. Thereafter, a reactive ion etch (RIE) process is used to etch the sacrificial layer 12 leaving behind sacrificial pillars beneath the photo-resist mask 13 as shown in FIG. 1c. In FIG. 1d, the photo-resist mask 13 is then removed. In FIG. 1e, an inter insulation layer 14 is deposited. Then the inter insulation layer 14 is planarized by either etch back or chemical-mechanical polishing (CMP) to make the top surface of the inter insulation layer 14 flush with the top, surface of the sacrificial layer 12 as shown in FIG. 1f. Finally, the sacrificial layer 12 is removed to form a vias or trench structure.
As can be seen from the above-mentioned prior art, it is necessary to deposit a silicon film of polycrystalline or amorphous as a sacrificial layer in the fabricating process. In order to increase the performance of the semiconductor device, the above-mentioned prior art or other conventional methods for fabricating a dual-damascene multilevel interconnection structure unavoidably have to use two dielectric layers and an etch stop layer between them.
This invention has been made to overcome the above-mentioned drawback of a conventional method for fabricating an interconnection structure. The primary object of this invention is to provide a method for fabricating vias and trenches in a dual-damascene multilevel interconnection structure of an integration circuit. In addition, the manufacturing method of the invention can be used not only in the dual-damascene process but also in other semiconductor interconnection processes.
According to the invention, the method for fabricating interconnection structure in an integration circuit comprises the following steps: (a) forming photo-resist patterns by providing a substrate and depositing a photo-resist layer on the substrate, wherein a first dielectric layer can be deposited on the substrate before depositing the photo-resist layer, (b) depositing a second dielectric layer at low temperature, (c) removing the second dielectric layer by chemical-mechanical polishing to remove the portion of the second dielectric layer that covers the photo-resist patterns and to expose the photo-resist patterns, (d) removing the photo-resist patterns, and (e) stabilizing the second dielectric layer by thermal curing.